1. Field of the Invention
The present invention relates to a bus structure for use in an information processing system and, more particularly, to a system bus for interprocessor communication among processing elements connected from the system bus.
2. Description of the Prior Art
A basic architectural feature of many information processing systems, that is, computer systems, is the use of a common system bus to interconnect a plurality of processing elements, such as CPUs, memories and input/output controllers, each of which is capable of the independent execution of data processing and handling operations. The system bus provides the means by which the processing elements communicate, that is, coordinate their operations and exchange information, such as data.
As such, the structure and operation of the system bus is central to the operation and performance of the system and several recurring problems are seen in the design of such system busses. For example, it may be necessary to expand or reconfigure the system bus to meet differing functional requirements of the system. Additionally, it is desirable to be able to reconfigure the system bus without requiring changes to the processing elements and that the recognition as simple to accomplish as possible in terms of the bus itself. Moreover, changes in the configuration of the system bus should not in themselves alter the operation of the system or the processing elements.
Another problem is the manner in which the processing elements determine priority of access to the system bus. In many systems, the relative priorities of access to the system bus of the processing elements is either hard-wired or otherwise determined by the physical location of the processing elements in the system. The simple addition of a processing element, for example, another input/output controller, may require substantial physical rearrangements to the system. Physical bus access determination methods are undesirable also in multi-processor systems wherein many, if not all, of the processing elements essentially require equal access to the system bus.
In an alternate common method of determining system bus access, the processing elements are provided with a means for contending for priority of access to the bus. This approach reduces the possible speed of operation of the system bus due to the overhead required by the contention process, and may result in some processing e-ements being locked out of access to the bus for unacceptably long periods.
Yet a further concern is the manner in which interprocessor communications are actually performed. In many systems, all communications are treated in the same manner, so that frequent types of communications cannot be executed in an accelerated manner, thereby again limiting the speed of the system bus.
In addition, in many systems the types of communications between the processing elements are fixed. As a result, it is difficult to provide for new types of communications or to expand those originally provided, so that any addition or expansion of communications must be fitted into the existing communications types. This in turn limits the flexibility of the system in adapting to new or expanded functions and may result in a degradation of system performance.
The present invention provides a system bus structure and operation having improvements and features which address the above described problems and limitations.